A novel VLSI architecture for multi-channel online spike sorting is presented in\nthis paper. In the architecture, the spike detection is based on nonlinear energy operator\n(NEO), and the feature extraction is carried out by the generalized Hebbian algorithm\n(GHA). To lower the power consumption and area costs of the circuits, all of the channels\nshare the same core for spike detection and feature extraction operations. Each channel\nhas dedicated buffers for storing the detected spikes and the principal components of that\nchannel. The proposed circuit also contains a clock gating system supplying the clock to\nonly the buffers of channels currently using the computation core to further reduce the power\nconsumption. The architecture has been implemented by an application-specific integrated\ncircuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the\nproposed architecture has lower power consumption and hardware area costs for real-time\nmulti-channel spike detection and feature extraction.
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